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solomon systech semiconductor technical data this document contains information on a new product. specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1818A rev 1.2 p 1/47 mar 2004 copyright ? 2004 solomon systech limited advance information 104 x 65 stn lcd segment / common driver with controller SSD1818A
solomon systech mar 2004 p 2/47 rev 1.2 SSD1818A table of contents 1. general description ......................................................................................................... .............. 5 2. features .................................................................................................................... ........................... 5 3. ordering information ........................................................................................................ ............ 5 4. block diagram ............................................................................................................... .................... 6 5. die pad arrangement ......................................................................................................... ............. 7 6. pin description............................................................................................................. .................... 10 7. functional block descriptions............................................................................................... 15 8. command table ............................................................................................................... ................. 23 9. command descriptions ........................................................................................................ ......... 28 10. maximum ratings ............................................................................................................ ............... 34 11. dc characteristics......................................................................................................... ............. 35 12. ac characteristics......................................................................................................... ............. 37 13. application examples ....................................................................................................... .......... 41 14. initialization routine ..................................................................................................... ............. 43 15. tab drawing ................................................................................................................ .................... 44
SSD1818A rev 1.2 p 3/47 mar 2004 solomon systech table of tables table 1 - ordering information ................................................................................................. ................. 5 table 2 - SSD1818A series bump die pad coordinates (bump center) ............................................... 8 table 3 - example of row pin assignment for programmable mux of SSD1818A ........................... 14 table 4 - graphic display data ram (gddram) address map with display start line set to 38h.. 20 table 5 - write command table (d/ c =0, r/ w ( wr )=0, e( rd )=1) ...................................................... 23 table 6 - extended command table (d/ c = 0,r/ w ( wr ) = 0,e=1( rd = 1) unless specific setting is stated) ........................................................................................................................ ......................... 25 table 7 - automatic address increment .......................................................................................... ....... 27 table 8 - row pin assignment for com signals for SSD1818A in an 18 mux display (including icon line) without/with 7 lines display offset towards row0........................................................ 33 table 9 - maximum ratings (voltage referenced to v ss ) ..................................................................... 34 table 10 - dc characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = -30 to 85 c)........................................................................................................................ 35 table 11 - ac characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = -30 to 85 c)........................................................................................................................ 37 table 12 - interface timing characteristics (vdd - vss = 2.4 to 3.5v, ta = -35 to 85c) .................. 38 table 13 - interface timing characteristics (vdd - vss = 2.4 to 3.5v, ta = -35 to 85c) .................. 39 table 14 - interface timing characteristics (vdd - vss = 2.4 to 3.5v, ta = -35 to 85c) .................. 40
solomon systech mar 2004 p 4/47 rev 1.2 SSD1818A table of figures figure 1 - SSD1818A block diagram.............................................................................................. ........... 6 figure 2 - SSD1818A pin assignment............................................................................................. .......... 7 figure 3 - display data read back procedure - insertion of dummy read........................................ 15 figure 4 - oscillator .......................................................................................................... ........................ 16 figure 5 - dc-dc converter configurations...................................................................................... ..... 17 figure 6 - voltage regulator output for different gain/contrast settings.......................................... 18 figure 7 - lcd driving waveform for displaying "0" ............................................................................ 2 2 figure 8 - contrast control flow set segment re-map ........................................................................ 28 figure 9 - 6800-series mpu parallel interface characteristics ............................................................. 38 figure 10 - 8080-series mpu parallel interface characteristics ........................................................... 39 figure 11 - serial interface characteristics ................................................................................... ......... 40 figure 12 - application circuit of 104 x 64 plus an icon line using SSD1818A, configured with: external vee, internal regulator, divider mode enabled (command: 2b), 6800-series mpu parallel interface, internal oscillator and master mode ................................................................. 41 figure 13 - application circuit of 104 x 64 plus an icon line using SSD1818A, configured with all internal power control circuit enabled, 6800-series mpu parallel interface, internal oscillator and master mode. ............................................................................................................... ............... 42 figure 14 - SSD1818At copper view layout ....................................................................................... .. 44 figure 15 - SSD1818At pin assignment ........................................................................................... ..... 46
SSD1818A rev 1.2 p 5/47 mar 2004 solomon systech 1. general description SSD1818A is a single-chip cmos lcd driver with controllers for dot-matrix graphic liquid crystal display system. it consists of 169 high-voltage driving outputs for driving maximum 104 segments, 64 commons and 1 icon line. SSD1818A consists of 104 x 65 bits graphic display data ram (gddram). data/commands are sent from common mcu through 8-bit parallel or 4-wire serial interface. 6800-series, 8080-series compatible parallel interface and serial peripheral interface can be selected by hardware configuration. SSD1818A embeds dc-dc converter with booster capacitors, on-chip oscillator and bias divider so as to reduce the number of external components. with the advanced design for low power consumption, stable lcd operating voltage and flexible die layout, SSD1818A is suitable for any portable battery-driven applications requiring long operation period with compact size. 2. features maximum display size: 104 x 64 + 1 icon line single supply operation, 2.4 v - 3.5v minimum -12.0v lcd driving output voltage low current sleep mode on-chip voltage generator or external lcd driving power supply selectable 2x / 3x / 4x/ 5x on-chip dc-dc converter on-chip oscillator on-chip bias divider programmable bias ratio [1/4-1/9] 8-bit 6800-series parallel interface, 8-bit 8080-series parallel interface and serial peripheral interface on-chip 104 x 65 graphic display data ram row re-mapping and column re-mapping vertical scrolling display offset control 64 level internal contrast & external contrast control programmable lcd driving voltage temperature coefficients programmable mux ratio [2-64 mux] (partial display mode) available in gold bump die 3. ordering information table 1 - ordering information ordering part number seg com package form reference remark SSD1818Az 104 64 + 1 gold bump die figure 2 on page 7 - SSD1818Atr1 96 54 tab figure 14 on page 44 -
solomon systech mar 2004 p 6/47 rev 1.2 SSD1818A 4. block diagram figure 1 - SSD1818A block diagram icons row0 ~ row63 seg0 ~seg103 hv buffer cell level shifter display data latch gddram 104 x 65 bits display timing generator oscillator level selector lcd driving voltage generato r 2x/ 3x/ 4x/ 5 x dc/ dc converter, voltage regulator, contrast control, bias divider temperature compensation command decoder parallel / serial interface command interface mstat m dof m/s cl cls v ss v dd c 0 c 1 v l6 v l5 v l4 v l3 v l2 v dd d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 [sck] [sda] v ee v ss1 c 4n c 3n c 1p c 1n c 2n c 2p irs spi 1 cs cs2 res d/ c r/ w e c68/ 80 p/ s ( wr ) ( rd ) v f
SSD1818A rev 1.2 p 7/47 mar 2004 solomon systech 5. die pad arrangement figure 2 ? SSD1818A pin assignment gold bump alignment mark this alignment mark contains gold bump for ic bumping process alignment and i c identifications. no conductive tracks should be laid underneath this mark to avoid short circuit. note: 1. the gold bumps face up in this diagram 2. all dimensions in m and (0,0) is the center of the chip die size: 8.66 mm x 1.48 mm die thickness: 550 +/- 25 um bump pitch: 60 um [min] bump height: nominal 18 um tolerance: < 3 um within die pin #1 (-3878.7, 237.475) x 35 8.75 26.25 26.25 26.25 x center (-3876.1625, 323.6625) 26.25 26.25 26.25 26.25 52.5 x center (2751.9625, 323.6625) 26.25 26.25 26.25 12.6 center (3875.55, 149.275) 16.8 13.65 12.6 73.5 73.5 16.8 13.65 x 8.75 (2755.725, 237.475) 35 t2 t1 t0 /spi vss irs vdd c1 vss c0 vdd p/s c68/80 vss cls m/s vdd vf vl6 vl6 vl6 vl5 vl5 vl5 vl4 vl4 vl4 vee vl3 vl3 vl3 vl2 vl2 vl2 vee c4n c4n c4n c2p c2p c2p c2n c2n c2n vee c1n c1n c1n c1p c1p c1p c3n c3n c3n test2 vee vee vee vee vee vee vss1 vss1 vss1 vss1 vss1 vss vss vss test1 test0 vdd vdd vdd vdd vdd vdd vdd d7 d6 d5 d4 d3 d2 d1 d0 vdd e/rd r/w vss d/c vee vee /res vdd cs2 /cs1 vss /dof cl m mstat nc row11 row12 row13 row14 row15 row16 row17 row18 row19 row20 row21 row22 row23 row24 row25 row26 row27 row28 row29 row30 row31 nc row10 row9 row8 row7 row6 row5 row4 row3 row2 row1 row0 icons seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg92 seg93 seg94 seg95 seg96 seg97 seg98 seg99 seg100 seg101 seg102 seg103 row32 row33 row34 row35 row36 row37 row38 row39 row40 row41 row42 row43 nc row44 row45 row46 row47 row48 row49 row50 row51 row52 row53 row54 row55 row56 row57 row58 row59 row60 row61 row62 row62 icons nc 254 255 1 center: 2751.9625, 323.6625 center: -3876.1625, 323.6625 center: -3875.55, 149.275 size: 88.2 x 88.2 277 276 126 125 104 103 (-3878.7, 237.475) (2755.725, 237.475)
solomon systech mar 2004 p 8/47 rev 1.2 SSD1818A table 2 - SSD1818A series bump die pad coordinates (bump center) pad # signal x-pos y-pos pad # signal x-pos y-pos pad # signal x-pos y-pos 1 mstat -3873.80 -581.35 51 c3n -27.48 -581.35 101 t1 3799.95 -581.35 2 m -3797.50 -581.35 52 c1p 48.83 -581.35 102 t2 3876.25 -581.35 3 cl -3721.20 -581.35 53 c1p 125.13 -581.35 103 nc 4178.48 -655.03 4 dof -3644.90 -581.35 54 c1p 201.43 -581.35 104 row31 4178.48 -594.83 5 vss -3568.60 -581.35 55 c1n 277.73 -581.35 105 row30 4178.48 -534.63 6 cs -3492.30 -581.35 56 c1n 354.03 -581.35 106 row29 4178.48 -474.43 7 cs2 -3416.00 -581.35 57 c1n 430.33 -581.35 107 row28 4178.48 -414.23 8 vdd -3339.70 -581.35 58 vee 506.63 -581.35 108 row27 4178.48 -354.03 9 res -3263.40 -581.35 59 c2n 582.93 -581.35 109 row26 4178.48 -293.83 10 vee -3178.35 -581.35 60 c2n 659.23 -581.35 110 row25 4178.48 -233.63 11 vee -3102.05 -581.35 61 c2n 735.53 -581.35 111 row24 4178.48 -173.43 12 d/ c -3017.00 -581.35 62 c2p 811.83 -581.35 112 row23 4178.48 -113.23 13 vss -2940.70 -581.35 63 c2p 888.13 -581.35 113 row22 4178.48 -53.03 14 r/ w -2864.40 -581.35 64 c2p 964.43 -581.35 114 row21 4178.48 7.18 15 e/ rd -2788.10 -581.35 65 c4n 1040.73 -581.35 115 row20 4178.48 67.38 16 vdd -2711.80 -581.35 66 c4n 1117.03 -581.35 116 row19 4178.48 127.58 17 d0 -2635.50 -581.35 67 c4n 1193.33 -581.35 117 row18 4178.48 187.78 18 d1 -2557.63 -581.35 68 vee 1269.63 -581.35 118 row17 4178.48 247.98 19 d2 -2481.33 -581.35 69 vl2 1345.93 -581.35 119 row16 4178.48 308.18 20 d3 -2403.10 -581.35 70 vl2 1422.23 -581.35 120 row15 4178.48 368.38 21 d4 -2325.23 -581.35 71 vl2 1498.53 -581.35 121 row14 4178.48 428.58 22 d5 -2248.93 -581.35 72 vl3 1574.83 -581.35 122 row13 4178.48 488.78 23 d6 -2172.63 -581.35 73 vl3 1651.13 -581.35 123 row12 4178.48 548.98 24 d7 -2096.33 -581.35 74 vl3 1727.43 -581.35 124 row11 4178.48 609.18 25 vdd -2020.03 -581.35 75 vee 1803.73 -581.35 125 nc 4178.48 663.25 26 vdd -1943.73 -581.35 76 vl4 1880.03 -581.35 126 row10 3834.60 587.83 27 vdd -1867.43 -581.35 77 vl4 1956.33 -581.35 127 row9 3774.40 587.83 28 vdd -1791.13 -581.35 78 vl4 2032.63 -581.35 128 row8 3714.20 587.83 29 vdd -1714.83 -581.35 79 vl5 2108.93 -581.35 129 row7 3654.00 587.83 30 vdd -1638.53 -581.35 80 vl5 2185.23 -581.35 130 row6 3593.80 587.83 31 vdd -1562.23 -581.35 81 vl5 2261.53 -581.35 131 row5 3533.60 587.83 32 test0 -1485.93 -581.35 82 vl6 2337.83 -581.35 132 row4 3473.40 587.83 33 test1 -1409.63 -581.35 83 vl6 2414.13 -581.35 133 row3 3413.20 587.83 34 vss -1333.33 -581.35 84 vl6 2490.60 -581.35 134 row2 3353.00 587.83 35 vss -1257.03 -581.35 85 vf 2566.73 -581.35 135 row1 3292.80 587.83 36 vss -1180.73 -581.35 86 vdd 2651.78 -581.35 136 row0 3232.60 587.83 37 vss1 -1095.68 -581.35 87 m/ s 2728.08 -581.35 137 icons 3172.40 587.83 38 vss1 -1019.38 -581.35 88 cls 2804.38 -581.35 138 seg0 3112.20 587.83 39 vss1 -943.08 -581.35 89 vss 2880.68 -581.35 139 seg1 3052.00 587.83 40 vss1 -866.78 -581.35 90 c68/ 80 2956.98 -581.35 140 seg2 2991.80 587.83 41 vss1 -790.48 -581.35 91 p/ s 3033.28 -581.35 141 seg3 2931.60 587.83 42 vee -714.18 -581.35 92 vdd 3109.58 -581.35 142 seg4 2871.40 587.83 43 vee -637.88 -581.35 93 c0 3185.88 -581.35 143 seg5 2811.20 587.83 44 vee -561.58 -581.35 94 vss 3262.18 -581.35 144 seg6 2751.00 587.83 45 vee -485.28 -581.35 95 c1 3338.48 -581.35 145 seg7 2690.80 587.83 46 vee -408.98 -581.35 96 vdd 3414.78 -581.35 146 seg8 2630.60 587.83 47 vee -332.68 -581.35 97 irs 3491.08 -581.35 147 seg9 2570.40 587.83 48 test2 -256.38 -581.35 98 vss 3567.38 -581.35 148 seg10 2510.20 587.83 49 c3n -180.08 -581.35 99 spi 3643.68 -581.35 149 seg11 2450.00 587.83 50 c3n -103.78 -581.35 100 t0 3723.65 -581.35 150 seg12 2389.80 587.83
SSD1818A rev 1.2 p 9/47 mar 2004 solomon systech pad # signal x-pos y-pos pad # signal x-pos y-pos pad # signal x-pos y-pos 151 seg13 2329.60 587.83 201 seg63 -680.40 587.83 251 row41 -3690.40 587.83 152 seg14 2269.40 587.83 202 seg64 -740.60 587.83 252 row42 -3750.60 587.83 153 seg15 2209.20 587.83 203 seg65 -800.80 587.83 253 row43 -3810.80 587.83 154 seg16 2149.00 587.83 204 seg66 -861.00 587.83 254 nc -4178.48 663.25 155 seg17 2088.80 587.83 205 seg67 -921.20 587.83 255 row44 -4178.48 609.18 156 seg18 2028.60 587.83 206 seg68 -981.40 587.83 256 row45 -4178.48 548.98 157 seg19 1968.40 587.83 207 seg69 -1041.60 587.83 257 row46 -4178.48 488.78 158 seg20 1908.20 587.83 208 seg70 -1101.80 587.83 258 row47 -4178.48 428.58 159 seg21 1848.00 587.83 209 seg71 -1162.00 587.83 259 row48 -4178.48 368.38 160 seg22 1787.80 587.83 210 seg72 -1222.20 587.83 260 row49 -4178.48 308.18 161 seg23 1727.60 587.83 211 seg73 -1282.40 587.83 261 row50 -4178.48 247.98 162 seg24 1667.40 587.83 212 seg74 -1342.60 587.83 262 row51 -4178.48 187.78 163 seg25 1607.20 587.83 213 seg75 -1402.80 587.83 263 row52 -4178.48 127.58 164 seg26 1547.00 587.83 214 seg76 -1463.00 587.83 264 row53 -4178.48 67.38 165 seg27 1486.80 587.83 215 seg77 -1523.20 587.83 265 row54 -4178.48 7.18 166 seg28 1426.60 587.83 216 seg78 -1583.40 587.83 266 row55 -4178.48 -53.03 167 seg29 1366.40 587.83 217 seg79 -1643.60 587.83 267 row56 -4178.48 -113.23 168 seg30 1306.20 587.83 218 seg80 -1703.80 587.83 268 row57 -4178.48 -173.43 169 seg31 1246.00 587.83 219 seg81 -1764.00 587.83 269 row58 -4178.48 -233.63 170 seg32 1185.80 587.83 220 seg82 -1824.20 587.83 270 row59 -4178.48 -293.83 171 seg33 1125.60 587.83 221 seg83 -1884.40 587.83 271 row60 -4178.48 -354.03 172 seg34 1065.40 587.83 222 seg84 -1944.60 587.83 272 row61 -4178.48 -414.23 173 seg35 1005.20 587.83 223 seg85 -2004.80 587.83 273 row62 -4178.48 -474.43 174 seg36 945.00 587.83 224 seg86 -2065.00 587.83 274 row63 -4178.48 -534.63 175 seg37 884.80 587.83 225 seg87 -2125.20 587.83 275 icons -4178.48 -594.83 176 seg38 824.60 587.83 226 seg88 -2185.40 587.83 276 nc -4178.48 -655.03 177 seg39 764.40 587.83 227 seg89 -2245.60 587.83 277 nc -3875.55 149.28 178 seg40 704.20 587.83 228 seg90 -2305.80 587.83 179 seg41 644.00 587.83 229 seg91 -2366.00 587.83 180 seg42 583.80 587.83 230 seg92 -2426.20 587.83 181 seg43 523.60 587.83 231 seg93 -2486.40 587.83 182 seg44 463.40 587.83 232 seg94 -2546.60 587.83 183 seg45 403.20 587.83 233 seg95 -2606.80 587.83 184 seg46 343.00 587.83 234 seg96 -2667.00 587.83 bump size 185 seg47 282.80 587.83 235 seg97 -2727.20 587.83 pad# x [um] y [um] 186 seg48 222.60 587.83 236 seg98 -2787.40 587.83 1 ? 102 50.05 50.05 187 seg49 162.40 587.83 237 seg99 -2847.60 587.83 103 ? 124 66.675 40.95 188 seg50 102.20 587.83 238 seg100 -2907.80 587.83 125 66.675 28.7 189 seg51 42.00 587.83 239 seg101 -2968.00 587.83 126 ? 253 40.95 66.675 190 seg52 -18.20 587.83 240 seg102 -3028.20 587.83 254 66.675 28.7 191 seg53 -78.40 587.83 241 seg103 -3088.40 587.83 255 ? 276 66.675 40.95 192 seg54 -138.60 587.83 242 row32 -3148.60 587.83 277 88.2 88.2 193 seg55 -198.80 587.83 243 row33 -3208.80 587.83 194 seg56 -259.00 587.83 244 row34 -3269.00 587.83 195 seg57 -319.20 587.83 245 row35 -3329.20 587.83 196 seg58 -379.40 587.83 246 row36 -3389.40 587.83 197 seg59 -439.60 587.83 247 row37 -3449.60 587.83 198 seg60 -499.80 587.83 248 row38 -3509.80 587.83 199 seg61 -560.00 587.83 249 row39 -3570.00 587.83 200 seg62 -620.20 587.83 250 row40 -3630.20 587.83
solomon systech mar 2004 p 10/47 rev 1.2 SSD1818A 6. pin description mstat this pin is the static indicator driving output. it is only active in master operation. the frame signal output pin, m, should be used as the back plane signal for the static indicator. the duration of overlapping can be programmable. this pin, mstat, becomes high impedance if the chip is operating in slave mode. please see the extended command table for reference. m this pin is the frame signal input/output. in master mode, the pin supplies frame signal to slave devices. in slave mode, the pin receives frame signal from the master device. cl this pin is the system clock input/output. when the internal oscillator is enabled (cls pin pulled high), and the master mode is enabled (m/ s pin pulled high), this pin supplies system clock signal to the slave device. when internal oscillator is disabled and the slave mode is enabled, the pin receives system clock signal from the master device or external clock source. dof this pin is the display blanking signal control pin. in master mode, this pin supplies ?display on? or ?display off? signal (blanking signal) to slave devices. in slave mode, this pin receives ?display on? or ?display off? signal from the master device. 1 cs , cs2 these pins are the chip select inputs. the chip is enabled for mcu communication only when 1 cs is pulled low and cs2 is pulled high. res this pin is the reset signal input. initialization of the chip is started once this pin is pulled low. minimum pulse width for completing the reset procedure is 5 - 10us. d/ c this pin is data/command control pin. when the pin is pulled high, the input at d 7 -d 0 is treated as display data. when the pin is pulled low, the input at d 7 -d 0 will be transferred to the command register. for detailed relationship with other mcu interface signals, please refer to the timing characteristics diagrams. r/ w ( wr ) this pin is mcu interface input. when 6800 interface mode is selected, this pin will be used as read/write (r/ w ) selection input. read mode will be carried out when this pin is pulled high and write mode when this pin is pulled low. when 8080 interface mode is selected, this pin will be the write ( wr ) input. data write operation is initiated when this pin is pulled low and the chip is selected. e( rd ) this pin is mcu interface input. when 6800 interface mode is selected, this pin will be used as the enable (e) signal. read/ write operation is initiated when this pin is pulled high and the chip is selected. when 8080 interface mode is selected, this pin receives the read ( rd ) signal. data read operation is initiated when this pin is pulled low and the chip is selected.
SSD1818A rev 1.2 p 11/47 mar 2004 solomon systech d 7 -d 0 these pins are the 8-bit bi-directional data bus in parallel interface mode. d 7 is the msb while d 0 is the lsb. when serial mode is selected, d 7 is the serial data input (sda) and d 6 is the serial clock input (sck). v dd these pins are the chip?s power supply pins. these pins are also act as the reference for the dc-dc converter output and the lcd driving voltages. v ss these pins are the grounding of the chip. they are also act as the reference for the logic pins. v ss1 these pins are the inputs for internal dc-dc converter. the voltage of generated, v ee , equals to the multiple factors times the potential different between these pins, v ss1 , and v dd . the multiple factors, 2x, 3x, 4x or 5x are selected by different connections of the external capacitors. all voltage levels are referenced to v dd . note: the potential of vss 1 at this input pin must lower than or equal to v ss . v ee this is the most negative voltage supply pin of the chip. it can be supplied externally or generated by the internal dc-dc converter. the internal dc-dc converter is turned on when the internal voltage booster option is enabled. please refer to the set power control register command for detail description. when using internal dc-dc converter as voltage generator, voltage at this pin is used for internal referencing only. it cannot be used for driving external circuitry. c 1p , c 1n , c 2n , c 2p c 3n and c 4n when internal dc-dc voltage converter is used, external capacitor(s) is/are connected between these pins. different connections result in different dc-dc converter multiple factors, for example, 2x, 3x, 4x or 5x. for detailed connections, please refer to the voltage converter section in the functional block description. v l2 , v l3 , v l4 and v l5 these pins are outputs with voltage levels equal to the lcd driving voltage. all these voltage levels are referenced to v dd . the voltage levels can be supplied externally or generated by the internal bias divider. the bias divider is turned on when the output op-amp buffers are enabled. please refer to the set power control register command for detail description. the voltage potential relationship of these pins are given as: v dd > v l2 > v l3 > v l4 > v l5 > v l6 in addition, assume the bias factor is known as a, vl2 - vdd = 1/a * (vl6 - vdd) vl3 - vdd = 2/a * (vl6 - vdd) vl4 - vdd = (a-2)/a * (vl6 - vdd) vl5 - vdd = (a-1)/a * (vl6 - vdd) v l6 this pin outputs the most negative lcd driving voltage level. the v l6 can be supplied externally or generated by the internal regulator. please refer to the set power control register command for detail description.
solomon systech mar 2004 p 12/47 rev 1.2 SSD1818A m/ s this pin is the master/slave mode selection input. when this pin is pulled high, master mode is selected. cl, m, mstat and dof signals will be the output pins for slave devices. when this pin is pulled low, slave mode is selected. cl, m, dof are input pins getting signal from master device. the state of mstat will be high impedance. v f this pin is the input of the built-in voltage regulator for generating v l6 . when external resistor network is selected (irs pulled low) to generate the lcd driving level, v l6 , two external resistors should be added. r 1 should be connected between v dd and v f . r 2 should be connected between v f and v l6. cls this pin is the internal clock enable pin. when this pin is pulled high, internal clock is enabled. the internal clock will be disabled when cls is pulled low. under such circumstances, an external clock source must be fed into the cl pin. c68/ 80 this pin is the mcu parallel interface selection input. when the pin is pulled high, 6800 series interface is selected. when the pin is pulled low, 8080 series interface is selected. if serial interface is selected (p/ s pulled low), the setting of this pin is ignored. the c68 / 80 pin must be connected to a known logic state (either high or low). p/ s this pin is the serial/parallel interface selection input. when this pin is pulled high, parallel interface mode is selected. when this pin is pulled low, serial interface will be selected. note1: for serial mode, d0, d1, d2, d3, d4, d5, r/ w ( wr ), e/( rd ) are recommended to connect to vss. note2: read back operation is only available in parallel mode. c1, c0 these pins are the chip mode selection input. the chip mode is determined by multiplex ratio. altogether there are four chip modes. please see the following list for reference. c1 c0 chip mode 0 0 48 mux mode 0 1 54 mux mode 1 0 32 mux mode 1 1 64 mux mode irs this is the input pin to enable the internal resistors network for the voltage regulator. when this pin is pulled high, the internal feedback resistors of the internal regulator for generating v l6 will be enabled. when it is pulled low, external resistors, r 1 should be connected to v dd and v f . r 2 should be connected between v f and v l6 , respectively.
SSD1818A rev 1.2 p 13/47 mar 2004 solomon systech spi this is the input pin to enable the circuitry for providing serial interface. this pin must be connected to low at any circumstances. when the spi pin and the p/ s , selection input are both pulled low, the serial interface is enabled. when the spi pin is pulled low and the p/ s selection input is pulled high, the parallel interface is enabled. nc/test0 ? test2/t0 ? t2 these are the no connection pins. these pins should be left open individually. remarks: these pins should not be connected together. row0 - row63 these pins provide the common driving signals to the lcd panel. please refer to the table 3 on page 11 for the com signal mapping. seg0 - seg103 these pins provide the lcd segment driving signals. the output voltage level of these pins is v dd during sleep mode or standby mode. icons there are two icons pins (pin137 and 275) on the chip. both pins output exactly the same signal. the reason for duplicating these pins is to enhance the flexibility of the lcd layout.
solomon systech mar 2004 p 14/47 rev 1.2 SSD1818A table 3 ? example of row pin assignment for programmable mux of SSD1818A 48 mux mode 54 mux mode 32 mux mode 64 mux mode row0 nc nc nc com0 row1 nc nc nc com1 row2 nc nc nc com2 row3 nc nc nc com3 row4 nc nc nc com4 row5 nc com0 nc com5 row6 nc com1 nc com6 row7 nc com2 nc com7 row8 com0 com3 nc com8 row9 com1 com4 nc com9 row10 com2 com5 nc com10 row11 com3 com6 nc com11 row12 com4 com7 nc com12 row13 com5 com8 nc com13 row14 com6 com9 nc com14 row15 com7 com10 nc com15 row16 com8 com11 com0 com16 row17 com9 com12 com1 com17 row18 com10 com13 com2 com18 row19 com11 com14 com3 com19 row20 com12 com15 com4 com20 row21 com13 com16 com5 com21 row22 com14 com17 com6 com22 row23 com15 com18 com7 com23 row24 com16 com19 com8 com24 row25 com17 com20 com9 com25 row26 com18 com21 com10 com26 row27 com19 com22 com11 com27 row28 com20 com23 com12 com28 row29 com21 com24 com13 com29 row30 com22 com25 com14 com30 row31 com23 com26 com15 com31 row32 com24 com27 com16 com32 row33 com25 com28 com17 com33 row34 com26 com29 com18 com34 row35 com27 com30 com19 com35 row36 com28 com31 com20 com36 row37 com29 com32 com21 com37 row38 com30 com33 com22 com38 row39 com31 com34 com23 com39 row40 com32 com35 com24 com40 row41 com33 com36 com25 com41 row42 com34 com37 com26 com42 row43 com35 com38 com27 com43 row44 com36 com39 com28 com44 row45 com37 com40 com29 com45 row46 com38 com41 com30 com46 row47 com39 com42 com31 com47 row48 com40 com43 nc com48 row49 com41 com44 nc com49 row50 com42 com45 nc com50 row51 com43 com46 nc com51 row52 com44 com47 nc com52 row53 com45 com48 nc com53 row54 com46 com49 nc com54 row55 com47 com50 nc com55 row56 nc com51 nc com56 row57 nc com52 nc com57 row58 nc com53 nc com58 row59 nc nc nc com59 row60 nc nc nc com60 row61 nc nc nc com61 row62 nc nc nc com62 row63 nc nc nc com63 note: nc - row pin will output non-selected com signal
SSD1818A rev 1.2 p 15/47 mar 2004 solomon systech 7. functional block descriptions command decoder and command interface this module determines whether the input signal is interpreted as data or command. input is directed to this module based on the input of the d/ cpin. if the d/ c pin is high, input is written to graphic display data ram (gddram). if it is low, the input at d 7 -d 0 is interpreted as a command. it will be decoded and written to the corresponding command register. mpu parallel 6800-series interface the parallel interface consists of 8 bi-directional data pins (d 7 -d 0 ), r/ w ( wr ), d/ c, e/( rd ), 1 cs and cs2. read cycle r/ w ( wr ) input high indicates a read operation from the graphic display data ram (gddram) or the status register. in order to match the operating frequency of the gddram with that of the mcu, pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. this is shown in figure 3. figure 3 - display data read back procedure - insertion of dummy read write cycle r/ w ( wr ) input low indicates a write operation to display data ram or internal command registers depending on the d/ c input. the e( rd ) input serves as data latch signal (clock) when high, provided that 1 cs is pulled low and the cs2 is pulled high respectively. please refer to figure 9 on page 38 for parallel interface timing diagram of 6800-series microprocessors. mpu parallel 8080-series interface the parallel interface consists of 8 bi-directional data pins (d 7 -d 0 ), e/( rd ), r/ w ( wr ), d/ c, 1 cs and cs2. r / w ( wr ) e(rd) data bus write column address dummy read data read1 data read 2 data read 3 n n n+1 n+2
solomon systech mar 2004 p 16/47 rev 1.2 SSD1818A read cycle e( rd ) input serves as data read latch signal (clock) when low, provided that 1 cs is pulled low and the cs2 is pulled high respectively. the d / c signal determines whether the receiving signal is a display data read or a status register read signal. similar to 6800-series interface, a dummy read is also required before the first actual display data read. write cycle r/ w ( wr ) input serves as data write latch signal (clock) when high, provided that 1 cs and cs2 are low and high respectively. the d / c signal determines whether the receiving signal is a display data write or a command register write signal. please refer to figure 10 on page 39 for parallel interface timing diagram of 8080-series microprocessor. mpu serial interface the serial interface consists of serial clock sck (d 6 ), serial data sda (d 7 ), d / c , 1 cs and cs2. input to sda is shifted into a 8-bit shift register on every rising edge of sck in the order of d 7 , d 6 ,... d 0 . d / c is sampled on every eighth clock to determine whether the data byte in the shift register is written to the display data ram or command register at the same clock. oscillator circuit this module is an on-chip low power rc oscillator circuitry (figure 4). the oscillator generates the clock for the dc-dc voltage converter. this clock is also used in the display timing generator. enable oscillation circuit enable buffer internal resistor osc2 osc1 oscillator enable (cl) figure 4 - oscillator lcd driving voltage generator and regulator this module generates the lcd voltage required for display driving output. with reference to v dd , it takes a single supply input, v ss , and generates necessary voltage levels. this block consists of: 1. 2x, 3x, 4x and 5x dc-dc voltage converter the built-in dc-dc voltage converter is used to generate the negative voltage with reference to vdd from the voltage input (vss1). for SSD1818A, it is possible to produce 2x, 3x, 4x or 5x boosting from the potential different between v ss1 - v dd . detailed configurations of the dc-dc converter for different boosting multiples are given in figure 5.
SSD1818A rev 1.2 p 17/47 mar 2004 solomon systech figure 5 - dc-dc converter configurations 2. voltage regulator (voltages referenced to v dd ) internal (irs pin = h) feedback gain can control the lcd driving contrast curves. if internal resistor network is enabled, eight settings can be selected through software command. if external control is selected, external resistors are connected between v dd and v f (r1), and between v f and v l6 (r2). 3. contrast control (voltage referenced to v dd ) software control of the 64-contrast voltage levels at each voltage regulator feedback gain. the equation of calculating the lcd driving voltage is given as: v l6 ?v dd = gain * [1 + (18 + )] * v ref 81 stands for the contrast set (0 to 63) SSD1818A 5x boosting configuration v ss1 v ee c 3n c 1p c 1n c 2n c 2p c 4n c1 + + + c1 c1 c1 + + c1 4x boosting configuration v ss1 v ee c 3n c 1p c 1n c 2n c 2p c 4n c1 + + + c1 c1 + SSD1818A 3x boosting configuration v ss1 v ee c 3n c 1p c 1n c 2n c 2p c 4n c1 + + c1 c1 + SSD1818A 2x boosting configuration v ss1 v ee c 3n c 1p c 1n c 2n c 2p c 4n c1 + + c1 SSD1818A remarks: 1. c1= 0.47 ? 4.7uf 2. boosting input from v ss1 3. v ss1 should be lower potential than or equal to v ss 4. all voltages are referenced to v dd c1
solomon systech mar 2004 p 18/47 rev 1.2 SSD1818A gain = (1 + rb/ra), the reference value is shown in table 5. register ratio d2 d1 d0 thermal gradient = -0.07 %/ o c 0 0 0 2.92 0 0 1 3.40 0 1 0 3.89 0 1 1 4.37 1 0 0 4.85 1 0 1 5.23 1 1 0 5.72 1 1 1 6.19 gain value at different register ratio and thermal gradient settings v ref is a fixed ic?internal voltage supply and its voltage at room temperature (25 o c) is shown in table 6 for reference. type thermal gradient v ref tc 0 -0.07 %/ o c -1.090v tc 2 -0.13 %/ o c -1.089v tc 4 -0.26 %/ o c -1.065v tc 7 -0.29 %/ o c -1.071v external resistor gain mode [gain = 5.00] @ tc0 -0.07 %/ o c -1.090v v ref values at different thermal gradient settings the voltage regulator output for different gain/contrast settings is shown in figure 6. figure 6? voltage regulator output for different gain/contrast settings
SSD1818A rev 1.2 p 19/47 mar 2004 solomon systech ss d181 5 b v dd v l2 v l3 v l4 v l5 v l6 r3 r1 r2 r4 + v dd c5 + c4 + c3 + c2 + c1 r em a rk: 1. c1 ~ c 5 = 0 .01 ~ 0. 47u f 2. r1 ~ r4 = 100 k~ 1m ? SSD1818A 4. bias ratio selection circuitry the bias ratios can be software selected from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9. since there will be slightly different in command pattern for different mux, please refer to command descriptions section of this data sheet. if the output op-amp buffer option in set power control register command is enabled, this circuit block will divide the regulator output (v l6 ) to give the lcd driving levels (v l2 ~ v l5 ). a low power consumption circuit design in this bias divider saves most of the display current comparing to the traditional design. stabilizing capacitors (0.1uf ~ 0.47uf) are required to be connected between these voltage level pins (v l2 ~ v l5 ) and (v dd ). if the lcd panel loading is heavy, four additional resistors are suggested to add to the application circuit as follows: 5. self adjust temperature compensation circuitry this block provides 4 different compensation settings to satisfy various liquid crystal temperature grades by software control. default temperature coefficient (tc) setting is tc0. graphic display data ram (gddram) the gddram is a bit mapped static ram holding the bit pattern to be displayed. the size of the ram is 104 x 65 = 6760 bits. table 4 on page 20 is a description of the gddram address map. for mechanical flexibility, re-mapping on both segment and common outputs can be selected by software. for vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the ram data to be mapped to the display. table 4 on page 20 shows the case in which the display start line register is set to 38h. for those gddram out of the display common range, they could still be accessed, for either preparation of vertical scrolling data or even for the system usage. remark: 1. c1 ~ c5 = 0.1uf ~ 0.47uf 2. r1 ~ r4 = 100k ? ~1m ?
solomon systech mar 2004 p 20/47 rev 1.2 SSD1818A normal 00h 01h 02h 03h ? ? ? ? ? ? 64h 65h 66h 67h remapped 67h 66h 65h 64h ? ? ? ? ? ? 03h 02h 01h 00h 00h d0 (lsb) ? ? ? ? ? ? 8 39 8 45 8 23 8 55 01h d1 ? ? ? ? ? ? 9 38 9 44 9 22 9 54 02h d2 ? ? ? ? ? ? 1037104310211053 03h d3 ? ? ? ? ? ? 1136114211201152 04h d4 ? ? ? ? ? ? 1235124112191251 05h d5 ? ? ? ? ? ? 1334134013181350 06h d6 ? ? ? ? ? ? 1433143914171449 07h d7 (msb) ? ? ? ? ? ? 1532153815161548 08h d0 (lsb) ? ? ? ? ? ? 1631163716151647 09h d1 ? ? ? ? ? ? 1730173617141746 0ah d2 ? ? ? ? ? ? 1829183518131845 0bh d3 ? ? ? ? ? ? 1928193419121944 0ch d4 ? ? ? ? ? ? 2027203320112043 0dh d5 ? ? ? ? ? ? 2126213221102142 0eh d6 ? ? ? ? ? ? 2225223122 9 2241 0fh d7 (msb) ? ? ? ? ? ? 23 24 23 30 23 8 23 40 10h d0 (lsb) ? ? ? ? ? ? 24 23 24 29 24 7 24 39 11h d1 ? ? ? ? ? ? 2522252825 6 2538 12h d2 ? ? ? ? ? ? 2621262726 5 2637 13h d3 ? ? ? ? ? ? 2720272627 4 2736 14h d4 ? ? ? ? ? ? 2819282528 3 2835 15h d5 ? ? ? ? ? ? 2918292429 2 2934 16h d6 ? ? ? ? ? ? 3017302330 1 3033 17h d7 (msb) ? ? ? ? ? ? 31 16 31 22 31 0 31 32 18h d0 (lsb) ? ? ? ? ? ? 32 15 32 21 x x 32 31 19h d1 ? ? ? ? ? ? 33 14 33 20 x x 33 30 1ah d2 ? ? ? ? ? ? 34 13 34 19 x x 34 29 1bh d3 ? ? ? ? ? ? 35 12 35 18 x x 35 28 1ch d4 ? ? ? ? ? ? 36 11 36 17 x x 36 27 1dh d5 ? ? ? ? ? ? 37 10 37 16 x x 37 26 1eh d6 ? ? ? ? ? ? 38 9 38 15 x x 38 25 1fh d7 (msb) ? ? ? ? ? ? 39 8 39 14 x x 39 24 20h d0 (lsb) ? ? ? ? ? ? 40 7 40 13 x x 40 23 21h d1 ? ? ? ? ? ? 41 6 41 12 x x 41 22 22h d2 ? ? ? ? ? ? 42 5 42 11 x x 42 21 23h d3 ? ? ? ? ? ? 43 4 43 10 x x 43 20 24h d4 ? ? ? ? ? ? 44 3 44 9 x x 44 19 25h d5 ? ? ? ? ? ? 45 2 45 8 x x 45 18 26h d6 ? ? ? ? ? ? 46 1 46 7 x x 46 17 27h d7 (msb) ? ? ? ? ? ? 47 0 47 6 x x 47 16 28h d0 (lsb) ? ? ? ? ? ? x x 48 5 x x 48 15 29h d1 ? ? ? ? ? ? x x 49 4 x x 49 14 2ah d2 ? ? ? ? ? ? x x 50 3 x x 50 13 2bh d3 ? ? ? ? ? ? x x 51 2 x x 51 12 2ch d4 ? ? ? ? ? ? x x 52 1 x x 52 11 2dh d5 ? ? ? ? ? ? x x 53 0 x x 53 10 2eh d6 ? ? ? ? ? ? xxxxxx549 2fh d7 (msb) ? ? ? ? ? ? xxxxxx558 30h d0 (lsb) ? ? ? ? ? ? xxxxxx567 31h d1 ? ? ? ? ? ? xxxxxx576 32h d2 ? ? ? ? ? ? xxxxxx585 33h d3 ? ? ? ? ? ? xxxxxx594 34h d4 ? ? ? ? ? ? xxxxxx603 35h d5 ? ? ? ? ? ? xxxxxx612 36h d6 ? ? ? ? ? ? xxxxxx621 37h d7 (msb) ? ? ? ? ? ? xxxxxx630 38h d0 (lsb) ? ? ? ? ? ? 0 47 0 53 0 31 0 63 39h d1 ? ? ? ? ? ? 1 46 1 52 1 30 1 62 3ah d2 ? ? ? ? ? ? 2 45 2 51 2 29 2 61 3bh d3 ? ? ? ? ? ? 3 44 3 50 3 28 3 60 3ch d4 ? ? ? ? ? ? 4 43 4 49 4 27 4 59 3dh d5 ? ? ? ? ? ? 5 42 5 48 5 26 5 58 3eh d6 ? ? ? ? ? ? 6 41 6 47 6 25 6 57 3fh d7 (msb) ? ? ? ? ? ? 7 40 7 46 7 24 7 56 page 8 d0 (lsb) ? ? ? ? ? ? icons icons icons icons icons icons icons icons segment pins 0 1 2 3 ? ? ? ? ? ? 100 101 102 103 page 6 page 7 normal remapped page 2 page 3 page 4 page 5 page 0 page 1 normal remapped normal remapped ram row ram column normal remapped common pins 48 mux mode 54 mux mode 32 mux mode 64 mux mode remarks : db0 ? db7 represent the data bit of the gddram table 4 - graphic display data ram (gddram) address map with display start line set to 38h
SSD1818A rev 1.2 p 21/47 mar 2004 solomon systech reset circuit this block includes power on reset (por) circuitry and the hardware reset pin, res . the por and hardware reset performs the same reset function. once res receives a reset pulse, all internal circuitry will start to initialize. minimum pulse width the reset sequence is 5 - 10us. status of the chip after reset is given by: display is turned off default display mode: 104 x 64 + 1 icon line normal segment and display data column address mapping (seg0 mapped to row address 00h) read-modify-write mode is off power control register is set to 000b shift register data clear in serial interface bias ratio is set to default: 1/9 static indicator is turned off display start line is set to gddram column 0 column address counter is set to 00h page address is set to 0 normal scan direction of the com outputs contrast control register is set to 20h test mode is turned off temperature coefficient is set to tc0 note: please find more explanation in the applications note attached at the back of the specification. display data latch this block is a series of latches carrying the display signal information. these latches hold the data, which will be fed to the hv buffer cell and level selector to output the required voltage level. 64 mux: 104 + 65 = 169 hv buffer cell (level shifter) hv buffer cell works as a level shifter, which translates the low voltage output signal to the required driving voltage. the output is shifted out with reference an internal frm clock that comes from the display timing generator. the level selector, which is synchronized with the internal m signal, gives the voltage levels. level selector level selector is a control of the display synchronization. display voltage levels can be separated into two sets and used with different cycles. synchronization is important since it selects the required lcd voltage level to the hv buffer cell, which in turn outputs the com or seg lcd waveform.
solomon systech mar 2004 p 22/47 rev 1.2 SSD1818A lcd panel driving waveform figure 7 is an example of how the common and segment drivers may be connected to a lcd panel. the waveforms illustrate the desired multiplex scheme. figure 7 - lcd driving waveform for displaying "0" com1 com2 com3 com4 com5 com6 com7 e g 1 e g 2 e g 3 e g 4 com0 e g 0 time slot com0 com1 seg0 seg1 m v dd v l2 v l3 v l4 v l5 v l6 v dd v l2 v l3 v l4 v l5 v l6 v dd v l2 v l3 v l4 v l5 v l6 v dd v l2 v l3 v l4 v l5 v l6 * note 1: n+1 is the number of multiplex ratio including icon. 1 2 3 4 5 6 7 8 9 . . . n +1 * 1 2 3 4 5 6 7 8 9 . . . n +1 * 1 2 3 4 5 6 7 8 9 . . n +1 * 1 2 3 4 5 6 7 8 9 . . . n +1 *
SSD1818A rev 1.2 p 23/47 mar 2004 solomon systech 8. command table table 5 - write command table ( d/ c =0, r/ w ( wr )=0, e( rd ) =1) d/c hex d7 d6 d5 d4 d3 d2 d1 d0 command description 0 0 0 0 0 x 3 x 2 x 1 x 0 00 ? 0f set lower column address set the lower nibble of the column address register using x 3 x 2 x 1 x 0 as data bits. the lower nibble of column address is reset to 0000b after por. 0 0 0 0 1 x 3 x 2 x 1 x 0 10 ? 1f set higher column address set the higher nibble of the column address register using x 3 x 2 x 1 x 0 as data bits. the higher nibble of column address is reset to 0000b after por. 0 20 ? 27 0 0 1 0 0 x 2 x 1 x 0 set internal gain resistor ratio feedback gain of the internal regulated dc-dc converter for generating vout increases as x 2 x 1 x 0 increased from 000b to 111b. after por, x 2 x 1 x 0 = 100b. 0 28 ? 2f 0 0 1 0 1 x 2 x 1 x 0 set power control register x 0 =0: turns off the output op-amp buffer (por) x 0 =1: turns on the output op-amp buffer x 1 =0: turns off the internal regulator (por) x 1 =1: turns on the internal regulator x 2 =0: turns off the internal voltage booster (por) x 2 =1: turns on the internal voltage booster 0 1 x 5 x 4 x 3 x 2 x 1 x 0 0 40 ? 7f set display start line set gddram display start line register from 0-63 using x 5 x 4 x 3 x 2 x 1 x 0 . display start line register is reset to 000000 after por. 0 81 1 0 0 0 0 0 0 1 * * x 5 x 4 x 3 x 2 x 1 x 0 0 00 ? 3f set contrast control register select contrast level from 64 contrast steps. contrast increases (vl6 decreases) as x 5 x 4 x 3 x 2 x 1 x 0 is increased from 000000b to 111111b. x 5 x 4 x 3 x 2 x 1 x 0 = 100000b after por. 0 a0 ? a1 1 0 1 0 0 0 0 x 0 set segment re-map x 0 =0: column address 00h is mapped to seg0 (por) x 0 =1: column address 67h is mapped to seg0 refer to table 4 on page 20 for example. 0 a2 ? a3 1 0 1 0 0 0 1 x 0 set lcd bias x 0 =0: por default bias 48 mux mode: 1/8 54 mux mode: 1/8.4 32 mux mode: 1/6 64 mux mode: 1/9 x 0 =1: alternate bias 48 mux mode: 1/6 54 mux mode: 1/6 32 mux mode: 1/5 64 mux mode: 1/7 for other bias ratio settings, see ?set 1/4 bias ratio? and ?set bias ratio? in extended command set.
solomon systech mar 2004 p 24/47 rev 1.2 SSD1818A note: ? * ? stands for don't care bit d/c hex d7 d6 d5 d4 d3 d2 d1 d0 command description 0 a4 ? a5 1 0 1 0 0 1 0 x 0 set entire display on/off x 0 =0: normal display (por) x 0 =1: entire display on 0 a6 ? a7 1 0 1 0 0 1 1 x 0 set normal/reverse display x 0 =0: normal display (por) x 0 =1: reverse display 0 ae ? af 1 0 1 0 1 1 1 x 0 set display on/off x 0 =0: turns off lcd panel (por) x 0 =1: turns on lcd panel 0 b0 ? b8 1 0 1 1 x 3 x 2 x 1 x 0 set page address set gddram page address (0-8) for read/write using x 3 x 2 x 1 x 0 0 c0 ? c8 1 1 0 0 x 3 * * * set com output scan direction x 3 =0: normal mode (por) x 3 =1: remapped mode, com0 to com [n-1] becomes com [n-1] to com0 when multiplex ratio is equal to n. see table 4 on page 20 for detail mapping. 0 e0 1 1 1 0 0 0 0 0 set read-modify- write mode read-modify-write mode will be entered in which the column address will not be increased during display data read. after por, read-modify-write mode is turned off. 0 e2 1 1 1 0 0 0 1 0 software reset initialize internal status registers. 0 ee 1 1 1 0 1 1 1 0 set end of read- modify-write mode exit read-modify-write mode. ram column address before entering the mode will be restored. after por, read-modify-write mode is off. 0 ac ? ad 1 0 1 0 1 1 0 x 0 0 00 ? 03 * * * * * * x 1 x 0 indicator display mode and set indicator on/off this second byte command is required only when ?set indicator on? command is sent. x 0 = 0: indicator off (por, second command byte is not required) x 0 = 1: indicator on (second command byte required) x 1 x 0 = 00: indicator off x 1 x 0 = 01: indicator on and blinking at ~1 second interval x 1 x 0 = 10: indicator on and blinking at ~1/2 second interval x 1 x 0 = 11: indicator on constantly 0 e3 1 1 1 0 0 0 1 1 nop command result in no operation. 0 f0 1 1 1 1 0 0 0 0 test mode reset reserved for ic testing. do not use. 0 f0 ? ff 1 1 1 1 * * * * set test mode reserved for ic testing. do not use. 0 ae 1 0 1 0 1 1 1 0 0 a5 1 0 1 0 0 1 0 1 set power save mode either standby or sleep mode will be entered using compound commands. issue compound commands ?set display off? followed by ?set entire display on?.
SSD1818A rev 1.2 p 25/47 mar 2004 solomon systech extended command table table 6 - extended command table (d/ c = 0,r/ w ( wr ) = 0,e=1( rd = 1) unless specific setting is stated) d/c hex d7 d6 d5 d4 d3 d2 d1 d0 command description 0 a8 1 0 1 0 1 0 0 0 0 x 6 x 5 x 4 x 3 x 2 x 1 x 0 0 00 ? 7f set multiplex ratio to select multiplex ratio n from 2 to the maximum multiplex ratio (por value) for each member (including icon line for 65 mux mode). max. mux ratio: 68 mux: 68 n = x 6 x 5 x 4 x 3 x 2 x 1 x 0 + 1 + icon*, (*icon exist for 64/54/32 mux mode) e.g. n = 001111b + 2 = 17 0 a9 1 0 1 0 1 0 0 1 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 0 00 ? ff set bias ratio (x 1 x 0 ) set tc value (x 4 x 3 x 2 ) modify osc. freq. (x 7 x 6 x 5 ) for 64 mux mode x 1 x 0 = 00(por) 01 10 11 1/9 or 1/7 1/5 1/6 1/8 for 54 mux mode x 1 x 0 = 00(por) 01 10 11 1/8.4 or 1/6 1/5 1/6 1/8 for 48 mux mode x 1 x 0 = 00(por) 01 10 11 1/8 or 1/6 1/5 1/6 1/8 for 32 mux mode x 1 x 0 = 00(por) 01 10 11 1/6 or 1/5 1/5 1/6 1/8 x 4 x 3 x 2 = 000: (tc0) typ. ?0.07 x 4 x 3 x 2 = 010: (tc2) typ. ?0.13 x 4 x 3 x 2 = 100: (tc4) typ. ?0.26 x 4 x 3 x 2 = 111: (tc7) typ. ?0.29 x 4 x 3 x 2 = 001, 011, 101, 110: reserved increase the value of x 7 x 6 x 5 will increase the oscillator frequency and vice versa. default mode: x 7 x 6 x 5 = 011 (por for 48 mux mode, 54 mux mode) : typ. 31.5khz x 7 x 6 x 5 = 011 (por for 32 mux mode, 64 mux mode) : typ. 18.7khz remarks: by software program the multiplex ratio, the typical oscillator frequency is listed above.
solomon systech mar 2004 p 26/47 rev 1.2 SSD1818A d/c hex d7 d6 d5 d4 d3 d2 d1 d0 command description 0 aa ? ab 1 0 1 0 1 0 1 x 0 set ? bias ratio x 0 = 0: use normal setting (por) x 0 = 1: fixed at 1/4 bias regardless of other bias setting commands 1 1 0 1 0 0 0 x 0 0 d0 ? d1 set smart icon mode smart icon mode used for low power application. x 0 = 0: smart icon mode disable (por) x 0 = 1: smart icon mode enable 0 d2 1 1 0 1 0 0 1 0 0 00 ? 60 0 x 6 x 5 * * * * * set phases of smart icon mode the contrast level of the smart icon is controlled by 4 phases. the more the total phases, the lower the contrast level. x 6 x 5 = 00: 5 phases x 6 x 5 = 01: 7 phases (por) x 6 x 5 = 10: 9 phases x 6 x 5 = 11: 16 phases 0 d4 1 1 0 1 0 1 0 0 0 00 ? 30 0 0 x 5 x 4 0 0 0 0 set total frame phases of static icon the on/off of the static icon is given by 3 phases / 1 phase overlapping of the m and mstat signals. this command set total phases of the m/mstat signals for each frame. the more the total phases, the lower the contrast level. x 5 x 4 = 00: 5 phases x 5 x 4 = 01: 7 phases x 5 x 4 = 10: 9 phases (por) x 5 x 4 = 11: 16 phases 0 d3 1 1 0 1 0 0 1 1 0 00 ? 3f 0 0 x 5 x 4 x 3 x 2 x 1 x 0 set display offset after por, x 5 x 4 x 3 x 2 x 1 x 0 = 0 a fter setting mux ratio less than default value, data will be displayed at center of display matrix. to move display towards row 0 by l, x 5 x 4 x 3 x 2 x 1 x 0 = l to move display away from row 0 by l, x 5 x 4 x 3 x 2 x 1 x 0 = 64-l note: max. value of l = (por default mux ratio ? display mux)/2 0 d6 1 1 0 1 0 1 1 0 0 3c ? 3f 0 0 1 1 1 1 x 1 x 0 enable band gap reference circuit x1x0 = 00 01(por) 10 11 100 ms 200 ms 400 ms 800 ms approx. band gap clock period recommendation: set the band gap clock period to approx. 200ms 0 00 - ff d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 status register read d 7 =0: indicates the driver is ready for command. d 7 =1: indicates the driver is busy. d 6 =0: indicates reverse segment mapping with column address. d 6 =1: indicates normal segment mapping with column address. d 5 =0: indicates the display is on. d 5 =1: indicates the display is off. d 4 =0: initialization is completed. d 4 =1: initialization process is in progress after res or software reset. d 3 d 2 d 1 d 0 = 1001 or 0011, the 4-bit is fixed to either 1001 or 0011 which could be used to identify as solomon systech device.
SSD1818A rev 1.2 p 27/47 mar 2004 solomon systech note: - ? * ? stands for don't care bit - command patterns other than that given in command table and extended command table are prohibited. otherwise, unexpected result will occur. data read / write to read data from the gddram, input high to r/ w ( wr ) pin and d/ c pin for 6800-series parallel mode, input low to e ( rd ) pin and high to d/ c pin for 8080-series parallel mode. no data read is provided in serial interface mode. in normal data read mode, gddram column address pointer will be increased by one automatically after each data read. however, no automatic increase will be performed in read-modify-write mode. also, a dummy read is required before first valid data is read. see figure 3 on page 15 in functional block descriptions section for detail waveform diagram. to write data to the gddram, input low to r/ w ( wr ) pin and high to d/ c pin for both 6800-series and 8080-series parallel mode. for serial interface mode, it is always in write mode. gddram column address pointer will be increased by one automatically after each data write. it should be noted that, after the automatic column address increment, the pointer would not wrap round to 0. the pointer will exit the memory address space after accessing the last column. therefore, the pointer should be re-initialized when progress to another page address d/ c r/ w ( wr ) action auto address increment 0 0 write command no 0 1 read status no 1 0 write data yes 1 1 read data yes table 7 - automatic address increment
solomon systech mar 2004 p 28/47 rev 1.2 SSD1818A 9. command descriptions set lower column address this command specifies the lower nibble of the 8-bit column address of the display data ram. the column address will be increased by each data access after it is pre-set by the mcu. set higher column address this command specifies the higher nibble of the 8-bit column address of the display data ram. the column address will be increased by each data access after it is pre-set by the mcu. set internal regulator resistors ratio this command is to enable any one of the eight internal resistor sets for different regulator gain when using internal regulator resistor network (irs pin pulled high). in other words, this command is used to select which contrast curve from the eight possible selections. please refer to functional block descriptions section for detail calculation of the lcd driving voltage. set power control register this command turns on/off the various power circuits associated with the chip. there are three related power sub-circuits could be turned on/off by this command. internal voltage booster is used to generate the negative voltage supply (v ee ) from the voltage input (v ss1 - v dd ). an external negative power supply is required if this option is turned off. internal regulator is used to generate the lcd driving voltage, v l6 , from the negative power supply, v ee . output op-amp buffer is the internal divider for dividing the different voltage levels (v l2 , v l3 , v l4 , v l5 ) from the internal regulator output, v l6 . external voltage sources should be fed into this driver if this circuit is turned off. set display start line this command is to set display start line register to determine starting address of display ram to be displayed by selecting a value from 0 to 63. with value equals to 0, d0 of page 0 is mapped to com0. with value equals to 1, d1 of page0 is mapped to com0 and so on. display start line values of 0 to 63 are assigned to page 0 to 7. please refer to table 4 on page 20 as an example for display start line set to 56 (38h). set contrast control register this command adjusts the contrast of the lcd panel by changing the lcd driving voltage, v l6 , provided by the on-chip power circuits. v l6 is set with 64 steps (6-bit) in the contrast control register by a set of compound commands. see figure 8 for the contrast control flow. figure 8 - contrast control flow set segment re-map n o yes changes complete? set contrast control register contrast level data
SSD1818A rev 1.2 p 29/47 mar 2004 solomon systech this command changes the mapping between the display data column addresses and segment drivers. it allows flexibility in mechanical layout of lcd glass design. please refer to table 4 on page 20 for example. set lcd bias this command is used to select a suitable bias ratio required for driving the particular lcd panel in use. the selectable values of this command for 64 mux are 1/9 or 1/7, for 54 mux are 1/8.4 or 1/6, for 48 mux are 1/8 or 1/6, for 32 mux are 1/6 or 1/5. for other bias ratio settings, extended commands should be used. set entire display on/off this command forces the entire display, including the icon row, to be illuminated regardless of the contents of the gddram. in addition, this command has higher priority than the normal/reverse display. this command is used together with ?set display on/off? command to form a compound command for entering power save mode. see ?set power save mode? later in this section. set normal/reverse display this command turns the display to be either normal or reverse. in normal display, a ram data of 1 indicates an illumination on the corresponding pixel, while in reverse display, a ram data of 0 will turn on the pixel. it should be noted that the icon line will not affect, that is not reverse by this command. set display on/off this command is used to turn the display on or off. when display off is issued with entire display is on, power save mode will be entered. see ?set power save mode? later in this section for details. set page address this command enters the page address from 0 to 8 to the ram page register for read/write operations. please refer to table 4 on page 20 for detail mapping. set com output scan direction this command sets the scan direction of the com output allowing layout flexibility in lcd module assembly. see table 4 on page 20 for the relationship between turning on or off of this feature. in addition, the display will have immediate effect once this command is issued. that is, if this command is sent during normal display, the graphic display will have vertical flipping effect. set read-modify-write mode this command puts the chip in read-modify-write mode in which: 1. column address is saved before entering the mode 2. column address is increased only after display data write but not after display data read. this read-modify-write mode is used to save the mcu?s loading when a very portion of display area is being updated frequently. as reading the data will not change the column address, it could be get back from the chip and do some operation in the mcu. then the updated data could be writing back to the gddram with automatic address increment. after updating the area, ?set end of read-modify-write mode? is sent to restore the column address and ready for next update sequence. software reset issuing this command causes some of the chip?s internal status registers to be initialized: read-modify-write mode is off static indicator is turned off
solomon systech mar 2004 p 30/47 rev 1.2 SSD1818A display start line register is cleared to 0 column address counter is cleared to 0 page address is cleared to 0 normal scan direction of the com outputs internal regulator resistors ratio is set to 4 contrast control register is set to 20h set end of read-modify-write mode this command relieves the chip from read-modify-write mode. the column address before entering read- modify-write mode will be restored no matter how much modification during the read-modify-write mode. set indicator on/off this command turns on or off the static indicator driven by the m and mstat pins. when the ?set indicator on? command is sent, the second command byte ?indicator display mode? must be followed. however, the ?set indicator off? command is a single byte command and no second byte command is required. the status of static indicator also controls whether standby mode or sleep mode will be entered, after issuing the power save compound command. see ?set power save mode? later in this section. nop a command causing the chip takes no operation. set test mode this command forces the driver chip into its test mode for internal testing of the chip. under normal operation, users should not use this command. set power save mode entering standby or sleep mode should be done by using a compound command composed of ?set display on/off? and ?set entire display on/off? commands. when ?set entire display on? is issued when display is off, either standby mode or sleep mode will be entered. the status of the static indicator will determine which power save mode is entered. if static indicator is off, the sleep mode will be entered: internal oscillator and lcd power supply circuits are stopped segment and common drivers output v dd level the display data and operation mode before sleep are held internal display ram can still be accessed if the static indicator is on, the chip enters standby mode, which is similar to sleep mode except addition with: internal oscillator is on static drive system is on please also be noted that during standby mode, if the software-reset command is issued, sleep mode will be entered. both power-save modes can be exited by the issue of a new software command or by pulling low at hardware pin res . status register read this command is issued by pulling d/ c low during a data read (refer to figure 9 on page 38 and figure 10 on page 39 for parallel interface waveforms). it allows the mcu to monitor the internal status of the chip. no status read is provided for serial mode.
SSD1818A rev 1.2 p 31/47 mar 2004 solomon systech extended commands these commands are used, in addition to basic commands, to trigger the enhanced features designed for the chip. set multiplex ratio this command switches default multiplex ratio to any multiplex mode from 2 to the maximum multiplex ratio (por value), including the icon line. max. mux ratio: 65 the chip pins row0-row63 will be switched to corresponding com signal output, see table 8 on page 33 for examples of 18 multiplex (including icon line) settings with and without 7 lines display offset for different mux. it should be noted that after changing the display multiplex ratio, the bias ratio might also need to be adjusted to make display contrast consistent. set bias ratio except the 1/4 bias, all other available bias ratios could be selected using this command plus the ?set lcd bias? command. for detail setting values and por default, please refer to the extended command table, table 6 on page 25. set temperature coefficient (tc) value one out of 4 different temperature coefficient settings is selected by this command in order to match various liquid crystal temperature grades. please refer to the extended command table, table 6 on page 25, for detailed tc values. modify oscillator frequency the oscillator frequency can be fine tuned by applying this command. since the oscillator frequency will be affected by some other factors, this command is not recommended for general usage. please contact solomon systech limited application engineers for more detail explanation on this command. set 1/4 bias ratio this command sets the bias ratio directly to 1/4. this bias ratio is especially designed for use in under 12 mux display. in order to restore to other bias ratio, this command must be executed, with lsb=0, before the ?set multiplex ratio? or ?set lcd bias? command is sent. set smart icon mode the smart icon mode is designed for the low power application. this command is used to enable the smart icon mode. set phases of smart icon mode the contrast level of the smart icon is controlled by 4 phases. the more the total phases, the shorter overlap time and thus the lower effective driving voltage. as a result, the contrast level of the smart icon will be lower. change of this smart icon mode phases will not affect the total frame phases of the static icon. they are independent commands. set total frame phases of static icon the total number of phases for one display frame is set by this command. the overlapping of the m and mstat signals generates the static icon. these two pins output either v ss or v dd at same frequency but with phase different.
solomon systech mar 2004 p 32/47 rev 1.2 SSD1818A to turn on the static icon, 3 phases overlapping is applied to these signals, while 1 phase overlapping is given to the off status. the more the total frame phases, the shorter overlap time and thus the lower effective driving voltage. as a result, the contrast level of the static icon will be lower. set display offset this command should be sent only when the multiplex ratio is set less than the default value. when a lesser multiplex ratio is set, the display will be mapped in the middle (y-direction) of the lcd, see the no offset columns on table 8 on page 33. use this command could move the display vertically within the 64 commons. to make the reduced-mux com 0 (com 0 after reducing the multiplex ratio) towards the row 0 direction for l lines, the 6-bit data in second command should be given by l. an example for 21 lines moving towards to com0 direction is given on table 8 on page 33. to move in the other direction by l lines, the 6-bit data should be given by 64-l. please note that the display is confined within the default multiplex value. that is the half of the default value minus the reduced-multiplex ratio gives the maximum value of l. for an odd display mux after reduction, moving away from row 0 direction will has 1 more step. enable band gap reference circuit this command enables or disables the band gap reference circuit. there are four selections on the band gap clock period. we recommended setting the band gap clock period to 200ms in normal operation.
SSD1818A rev 1.2 p 33/47 mar 2004 solomon systech 48 mux mode 54 mux mode 32 mux mode 64 mux mode no offset 7 lines offset no offset 7 lines offset no offset 7 lines offset no offset 7 lines offset row0 nc nc nc nc nc nc x x row1 nc nc nc nc nc nc x x row2 nc nc nc nc nc nc x com0 row3 nc nc nc nc nc nc x com1 row4 nc nc nc nc nc nc x com2 row5 nc nc x com3 nc nc x com3 row6 nc nc x com4 nc nc x com4 row7 nc nc x com5 nc nc x com5 row8 x com6 x com6 nc nc x com6 row9 x com7 x com7 nc nc x com7 row10 x com8 x com8 nc nc x com8 row11 x com9 x com9 nc nc x com9 row12 x com10 x com10 nc nc x com10 row13 x com11 x com11 nc nc x com11 row14 x com12 x com12 nc nc x com12 row15 x com13 x com13 nc nc x com13 row16 x com14 x com14 x com14 x com14 row17 x com15 x com15 x com15 x com15 row18 x com16 x com16 x com16 x com16 row19 x x x x x x x x row20 x x x x x x x x row21 x x x x x x x x row22 x x x x x x x x row23 com0 x com0 x com0 x com0 x row24 com1 x com1 x com1 x com1 x row25 com2 x com2 x com2 x com2 x row26 com3 x com3 x com3 x com3 x row27 com4 x com4 x com4 x com4 x row28 com5 x com5 x com5 x com5 x row29 com6 x com6 x com6 x com6 x row30 com7 x com7 x com7 x com7 x row31 com8 x com8 x com8 x com8 x row32 com9 x com9 x com9 x com9 x row33 com10 x com10 x com10 x com10 x row34 com11 x com11 x com11 com0 com11 x row35 com12 x com12 x com12 com1 com12 x row36 com13 x com13 x com13 com2 com13 x row37 com14 x com14 x com14 com3 com14 x row38 com15 x com15 x com15 com4 com15 x row39 com16 x com16 x com16 com5 com16 x row40 x x x x x com6 x x row41 x x x x x com7 x x row42 x x x x x com8 x x row43 x x x x x com9 x x row44 x x x x x com10 x x row45 x x x x x com11 x x row46 x x x x x com12 x x row47 x x x x x com13 x x row48 x x x x nc nc x x row49 x x x x nc nc x x row50 x com0 x x nc nc x x row51 x com1 x x nc nc x x row52 x com2 x x nc nc x x row53 x com3 x x nc nc x x row54 x com4 x x nc nc x x row55 x com5 x x nc nc x x row56 nc nc x com0 nc nc x x row57 nc nc x com1 nc nc x x row58 nc nc x com2 nc nc x x row59 nc nc nc nc nc nc x x row60 nc nc nc nc nc nc x x row61 nc nc nc nc nc nc x x row62 nc nc nc nc nc nc x x row63 nc nc nc nc nc nc x x table 8 - row pin assignment for com signals for SSD1818A in an 18 mux display (including icon line) without/with 21 lines display offset towards row0 note: x-row pin will output non-selected com signal
solomon systech mar 2004 p 34/47 rev 1.2 SSD1818A 10. maximum ratings table 9 - maximum ratings (voltage referenced to v ss ) symbol parameter value unit v dd -0.3 to +4.0 v v ee supply voltage 0 to ?12.0 v vin input voltage vss-0.3 to vdd+0.3 v i current drain per pin excluding v dd and v ss 25 ma t a operating temperature -30 to +85 o c t stg storage temperature -65 to +150 o c maximum ratings are those values beyond which damages to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description section this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that vdd and vee be constrained to the range vss < or = (vdd or vee) < or = vdd. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g ., either vss or vdd). unused outputs must be left open. this device may be light sensitive. caution should be taken to avoid exposure of this device to any light source during normal operation. this device is not radiation protected.
SSD1818A rev 1.2 p 35/47 mar 2004 solomon systech 11. dc characteristics table 10 - dc characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = -30 to 85 c) symbol parameter test condition min typ max unit v dd logic circuit supply voltage range recommend operating voltage possible operating voltage 2.4 2.7 3.5 v v i ac access mode supply current drain (v dd pins) v dd = 2.7v, voltage generator on, 4x dc-dc converter enabled, write accessing, tcyc =3.3mhz, typ. osc. freq., display on, no panel attached. - 480 600 a i dp1 display mode supply current drain (v dd pins) v dd = 2.7v, v ee = -8.1v, voltage generator disabled, r/ w ( wr ) halt, typ. osc. freq., display on, v l6 - v dd = -9v, no panel attached. - 50 100 a i dp2 display mode supply current drain (v dd pins) v dd = 2.7v, v ee = -8.1v, voltage generator on, 4x dc-dc converter enabled, r/ w ( wr ) halt, typ. osc. freq., display on, v l6 - v dd = -9v, no panel attached. - 120 200 a i sb standby mode supply current drain (v dd pins) v dd = 2.7v, lcd driving waveform off, typ. osc. freq., r/ w ( wr ) halt. - 5 10 a i sleep sleep mode supply current drain (v dd pins) v dd = 2.7v, lcd driving waveform off, oscillator off, r/ w ( wr ) halt. - 1 5 a v ee lcd driving voltage generator output (v ee pin) display on, voltage generator enabled, dc-dc converter enabled, typ. osc. freq., regulator enabled, divider enabled. -12.0 - -2.4 v v lcd lcd driving voltage input (v ee pin) voltage generator disabled. -12.0 - -2.4 v v oh1 logic high output voltage iout=-100ma 0.9*v dd - v dd v v ol1 logic low output voltage iout=100ma 0 - 0.1* v dd v v l6 lcd driving voltage source (v l6 pin) regulator enabled (v l6 voltage depends on int/ext contrast control) v ee -0.5 - v dd v v l6 lcd driving voltage source (v l6 pin) regulator disable - floating - v v ih1 logic high input voltage 0.8*v dd - v dd v v il1 logic low input voltage 0 - 0.2* v dd v
solomon systech mar 2004 p 36/47 rev 1.2 SSD1818A - 1/a*v l6 - v - 2/a*v l6 - v - (a-2)/a *v l6 - v - (a-1)/a *v l6 - v v l2 v l3 v l4 v l5 v l6 lcd display voltage output (v l2 , v l3 , v l4 , v l5 , v l6 pins) voltage reference to v dd , bias divider enabled, 1:a bias ratio - v l6 - v v l3 - v dd v v l4 - v l2 v v l5 - v l3 v v l6 - v l4 v v l2 v l3 v l4 v l5 v l6 lcd display voltage input (v l2 , v l3 ,v l4 , v l5 , v l6 pins) voltage reference to v dd , external voltage generator, bias divider disabled -12v - v l5 v i oh logic high output current source vout = v dd -0.4v 50 - - a i ol logic low output current drain vout = 0.4v - - -50 a i oz logic output tri-state current drain source -1 - 1 a i il /i ih logic input current -1 - 1 a c in logic pins input capacitance - 5 7.5 pf ? v l6 variation of v l6 output (v dd is fixed) regulator enabled, internal contrast control enabled, set contrast control register = 0 -3 0 3 % tc0 temperature coefficient compensation flat temperature coefficient (por) 0 -0.07 -0.11 %/ o c tc2 temperature coefficient 2* -0.11 -0.13 -0.15 %/ o c tc4 temperature coefficient 4* -0.15 -0.26 -0.28 %/ o c tc7 temperature coefficient 7* voltage regulator enabled -0.28 -0.29 -0.30 %/ o c the formula for the temperature coefficient is: tc(%) = v ref at 50 o c ? v ref at 0 o c x 1 x 100 % 50 o c ? 0 o c v ref at 25 o c
SSD1818A rev 1.2 p 37/47 mar 2004 solomon systech 12. ac characteristics table 11 - ac characteristics (unless otherwise specified, voltage referenced to v ss , v dd = 2.4 to 3.5v, t a = -30 to 85 c) symbol parameter test condition min typ max unit fosc oscillation frequency of display timing generator for: 64/32 mux mode: 54/48 mux mode: internal oscillator enabled (default), vdd = 2.7v remark: oscillation frequency vs. temperature change (-20c to 70c): -0.29%/c (64 mux), -0.31%/c (54/48 mux) and -0.24%/c (32 mux) 15.9 26.4 18.7 31.5 25.7 42.72 khz f frm frame frequency 64 mux mode 54 mux mode 48 mux mode 32 mux mode 104 x 64 graphic display mode, display on, internal oscillator enabled 104 x 64 graphic display mode, display on, internal oscillator disabled, external clock with freq., fext, feeding to cl pin. 104 x 54 graphic display mode, display on, internal oscillator enabled 104 x 54 graphic display mode, display on, internal oscillator disabled, external clock with freq., fext, feeding to cl pin. 104 x 48 graphic display mode, display on, internal oscillator enabled 104 x 48 graphic display mode, display on, internal oscillator disabled, external clock with freq., fext, feeding to cl pin. 104 x 32 graphic display mode, display on, internal oscillator enabled 104 x 32 graphic display mode, display on, internal oscillator disabled, external clock with freq., fext, feeding to cl pin. fosc 4x65 fext 4x65 fosc 8x54 fext 8x54 fosc 8x49 fext 4x49 fosc 8x33 fext 4x33 hz hz hz hz hz hz hz hz remarks: fext stands for the frequency value of external clock feeding to the cl pin fosc stands for the frequency value of internal oscillator frequency limits are based on the software command set: set multiplex ratio to 64 mux
solomon systech mar 2004 p 38/47 rev 1.2 SSD1818A symbol parameter min typ max unit t cycle clock cycle time 300 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 40 - - ns t dhw write data hold time 15 - - ns t dhr read data hold time 20 - - ns t oh output disable time - - 70 ns t acc access time - - 140 ns pw csl chip select low pulse width (read) chip select low pulse width (write) 120 60 - - - - ns pw csh chip select high pulse width (read) chip select high pulse width (write) 60 60 - - - - ns t r rise time - - 15 ns t f fall time - - 15 ns table 12 - interface timing characteristics (vdd - vss = 2.4 to 3.5v, ta = -35 to 85c) t oh t dhr t acc valid data valid data t dsw t dhw t r t f pw csl pw csh t cycle t ah t as d 0 -d 7 (read data from driver) d 0 -d 7 (write data to driver) cs1 cs2 = 1 e d/c r/w figure 9 - 6800-series mpu parallel interface characteristics
SSD1818A rev 1.2 p 39/47 mar 2004 solomon systech symbol parameter min typ max unit t cycle clock cycle time 300 - - ns t as address setup time 0 - - ns t ah address hold time 0 - - ns t dsw write data setup time 40 - - ns t dhw write data hold time 15 - - ns t dhr read data hold time 20 - - ns t oh output disable time - - 70 ns t acc access time - - 140 ns pw csl chip select low pulse width (read) chip select low pulse width (write) 120 60 - - - - ns pw csh chip select high pulse width (read) chip select high pulse width (write) 60 60 - - - - ns t r rise time - - 15 ns t f fall time - - 15 ns table 13 - interface timing characteristics (vdd - vss = 2.4 to 3.5v, ta = -35 to 85c) t oh t dhr t acc valid data valid data t dsw t dhw t r t f pw csl pw csh t cycle t ah t as d 0 -d 7 (read data from driver) d 0 -d 7 (write data to driver) wr rd cs1 cs2 = 1 d/c figure 10 - 8080-series mpu parallel interface characteristics
solomon systech mar 2004 p 40/47 rev 1.2 SSD1818A symbol parameter min typ max unit t cycle clock cycle time 250 - - ns t as address setup time 150 - - ns t ah address hold time 150 - - ns t dsw write data setup time 100 - - ns t dhw write data hold time 100 - - ns t clkl clock low time 100 - - ns t clkh clock high time 100 - - ns t css chip select setup time (for d7 input) 120 - - - - ns t csh chip select hold time (for d0 input) 60 - - - - ns t r rise time - - 15 ns t f fall time - - 15 ns table 14 - interface timing characteristics (vdd - vss = 2.4 to 3.5v, ta = -35 to 85c) t dsw valid data t css t dhw t r t f t cycle t ah t as d/c sda sck cs1 cs2 = 1 d/c t clkl t clkh cs1 (cs2 = 1) sda sck d7 d2 d3 d4 d5 d6 d1 d0 figure 11 - serial interface characteristics
SSD1818A rev 1.2 p 41/47 mar 2004 solomon systech 13. application examples logic pin connections not specified above: pins connected to vdd: cs2, e/ rd , m/ s , cls, c68/ 80 , p/ s , hpm pins connected to vss: vss1 pins floating: dof , cl figure 12 - application circuit of 104 x 64 plus an icon line using SSD1818A, configured with: external vee, internal regulator, divider mode enabled (command: 2b), 6800-series mpu parallel interface, internal oscillator and master mode display panel size 104 x 64 + 1 icons line SSD1818A ic 64 mux seg0..................................seg103 segment remapped [command: a1] icons com0 : : com10 com11 : : com30 com31 com32 com33 : : : : com63 icons com44 com45 : : : : : com63 icons com10 com11 : : com18 com19 : : com30 com31 com43............com32 g103............................seg0 icons com0 ........... remapped com scan directiion [command: c8] remapped com scan directiion [command: c8] d0-d7 /cs1 /res d/c r/w vss[gnd] vee irs external vneg = -9.5v vdd = 2.775v vl6 vl4 vl2 vl3 vl5 0.1 ~ 0.47 uf x 5
solomon systech mar 2004 p 42/47 rev 1.2 SSD1818A logic pin connections not specified above: pins connected to vdd: cs2, e/ rd , m/ s , cls, c68/ 80 , p/ s , hpm pins connected to vss: vss1 pins floating: dof , cl figure 13 - application circuit of 104 x 64 plus an icon line using SSD1818A, configured with all internal power control circuit enabled, 6800-series mpu parallel interface, internal oscillator and master mode. display panel size 104 x 64 + 1 icons line SSD1818A ic 64 mux (die face up) seg0.................................seg103 icons com0 : : com10 com11 : : com30 com31 com32 com33 : : : : com63 icons com44 com45 : : : : : com63 icons com10 com11 : : com18 com19 : : com30 com31 com43............com32 seg103............................seg0 icons com0 .......... . remapped com scan directiion [command: c8] remapped com scan directiion [command: c8] d0-d7 and control bus vss [gnd] 0.47 - 4.7uf x 5 5x boosting vss vee c3n c1p c1n c2n c2p c4n vdd = 2.775v vl6 vl4 vl2 vl3 vl5 0.1 ~ 0.47 uf x 5
SSD1818A rev 1.2 p 43/47 mar 2004 solomon systech 14. initialization routine command (hex) (refer to figure 12: all internal power control circuit enable) command (hex) (refer to figure 13: external v ee , internal regulator and divider enable) description 1 e2 e2 software reset 2 2f 2b set power control register 3 24 24 set internal resistor gain = 24h 4 81 20 81 20 set contrast level = 20h 5 d6 3d d6 3d enable band gap reference circuit set band gap clock period = 200ms 6 a0 a0 set column address is map to seg0 7 c0 c0 set row address is map to com0 8 a4 a4 set entire display on/off = normal display 9 a6 a6 set normal / reverse display = normal display 10 af af set display on example internal booster, regulator and divider are enabled. v op = approx. -8.573v with reference to v dd external booster, internal regulator and divider are enabled. v op = approx. -8.593v with reference to v dd
solomon systech mar 2004 p 44/47 rev 1.2 SSD1818A 15. tab drawing figure 14 - SSD1818At copper view layout
SSD1818A rev 1.2 p 45/47 mar 2004 solomon systech
solomon systech mar 2004 p 46/47 rev 1.2 SSD1818A SSD1818At detail descriptions figure 15 - SSD1818At pin assignment
SSD1818A rev 1.2 p 47/47 mar 2004 solomon systech solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does solomon systech assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typica ls" must be validated for each customer application by customer's technical experts. solomon systech does not convey any license under its patent rights nor the rights of others. solomon systech products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the solom on systech product could create a situation where personal injury or death may occur. should buyer purchase or use solomon systech products for any suc h unintended or unauthorized application, buyer shall indemnify and hold solomon systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech was negligent regard ing the design or manufacture of the part. http://www.solomon-systech.com

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